The present invention relates to a clock generation circuit for generating an internal clock signal synchronized with an external clock signal and moreover a DLL (Delay Locked Loop) circuit which can adjust a duty ratio and moreover to the technique which can effectively be utilized for the clock generation circuit for generating the clock signal to determine the output timing, for example, in the SDRAM (Synchronous Dynamic Random Access Memory).
In recent years, attention has been paid to the SDRAM of the DDR (Double Data Rate) system, as a means for realizing higher data transfer rate of the SDRAM, for inputting and outputting the data in the doubled transmission rate of the input clock. In view of realizing the input/output of data in the higher transmission rate, the DDR SDRAM mounts a clock generation circuit called a DLL and a SMD for the matching between the phases of external clock and data output. This phase matching is required to acquire the sufficient set-up time of the output data for external clock. When the phase of external clock is matched with the phase of data output, the time required until the data is outputted from the input of the read command becomes equal to the integer times of the period of the external clock.
The official gazette of the Japanese Published Unexamined Patent Application No. HEI 6(1994)-29835 discloses, as illustrated in FIG. 16, a loop type phase adjusting circuit including a rising phase difference detecting means 33 for generating the first control signal VC1 indicating a phase difference by detecting the rising phase difference between the reference clock signal CREF and internal clock signal CIN and a falling phase difference detecting means 34 for generating the second control signal VC2 indicating a phase difference by detecting the falling phase difference between both clock signals. Meanwhile, the official gazette of HEI 11(1999)-15555 discloses a synchronization circuit corresponding to the DDR specifications for respectively executing independent phase comparison operations of the internal clock signal ICLKT-2R of the clock system generated from the rising edge of external clock signal ECLK and the internal clock signals ICLKT-2F and ICLKB-2F of the clock system generated from the falling edge of external clock signal ECLK.
The official gazette of HEI 9(1997)-321614 (corresponding U.S. Pat. No. 5,883,534) discloses, as illustrated in FIG. 2, a clock supply device 501 which is provided between the DLL apparatus 1 and a clock driver 3 and includes a waveform shaping device 2 as a duty ratio recovery device for converting the input clock IN having the desired duty ratio to the clock having the duty ratio of 50%.
The official gazette of HEI 11(1999)-17529 discloses a DLL circuit which is formed of a basic clock generation unit, a phase detecting unit, a phase adjusting unit and a circuit DCC11 for adjusting the duty of output stage to 50%.
The official gazette of HEI 10(1998)-264649 discloses a frequency multiplying circuit which is formed of a phase frequency detector 30 as a phase difference detector for detecting phase difference between the input signal f1 and the signal fed back from a voltage-controlled delay circuit 32 explained later, a loop filter 31 for outputting a control signal depending on the phase difference detected with the phase frequency detector 30, the aforementioned voltage-controlled delay circuit 32 for changing a delaying coefficient of the input signal depending on the control signal from the loop filter 31 and feeding back this input signal to the phase frequency detector 30, the first SR flip-flop 33 for outputting the signal of duty ratio of 25% by receiving a pair of output signals among the signals frequency-divided four signals which are sequentially outputted from the voltage-controlled delay circuit 32, the second SR flip-flop 34 for outputting the signal of duty ratio of 25% by receiving a pair of output signals among the frequency-divided four signals which are sequentially outputted from the voltage-controlled delay circuit 32 and an OR gate 35 for outputting the signal of duty ratio of 50% with logical OR calculation of the outputs of these first and second SR flopxe2x80x94flop circuits 33, 34.
The official gazette of HEI 11(1999)-86545 (corresponding U.S. Pat. No. 5,939,913) discloses the DLL circuit applied to the SDRAM of the DDR system.
The official gazette of HEI 10(1998)-150350 discloses a phase synchronous circuit including a synchronous Miller delay type synchronous circuit for generating the clock signal synchronized with the rising edge of external clock and a synchronous Miller delay type synchronous circuit for generating the clock signal which is deviated by the half-period from the rising edge of external clock in order to obtain the internal clock of the desired duty ratio not depending on the waveform of external clock signal by combining these two output clock signals.
The DLL (Delay Locked Loop) circuit used as a clock generation circuit delays the input clock and controls a degree of delay in order to generate the clock having the desired phase. However, in the DLL circuit of the related art generates difference of a degree of delay at the rising edge and falling edge of the clock due to the influence of unbalance of the circuit operation in the process of delaying the clock and thereby there is a possibility for generation of difference in the duty ratio of the input clock (ratio of high level period for one period) and the duty ratio of the output clock (hereinafter, referred to only as duty). In order to prevent deviation of duty of clock, the phase must be controlled independently at the rising edge and falling edge of the clock.
As the DLL circuit for individually controlling the amount of delay at both edges, discussion has been made for a variable delay circuit for individually controlling the amount of delay of the rising edge and falling edge of the clock and a circuit of the system including a phase comparator corresponding to both edges and for effectuating the feedback to the variable delay circuit through independent phase comparison at both edges.
Moreover, the DLL circuit including two kinds of delay circuits for both rising and falling edges to individually control the amount of delay of both edges has also been discussed.
Although various circuit systems have been proposed as the variable delay circuit for DLL, the inventors of the present invention have also discussed additionally that the available circuit may be limited in the case of using the variable delay circuit which can individually control the amount of delay of both rising edge and falling edge in order to prevent deviation of duty of the clock. Therefore, since a degree of freedom of design flexibility is lowered and the performance of the DLL circuit is determined with the performance of the variable delay circuit, limitation in the kind of variable delay circuit means limitation of performance of the DLL circuit.
Meanwhile, when the two kinds of delay circuits for rising and falling edges of the clock are used, there rises a problem that the circuit area and current dissipation of the system mounting the DLL circuit increase because the circuit size and current dissipation increase remarkably.
An object of the present invention is to provide a clock generation circuit for eliminating deviation of duty of the output clock which interferes the phase control to realize high precision phase control only by adding a simplified circuit.
The aforementioned and the other objects and novel features of the present invention will become apparent from the description of the present invention and the attached drawings thereof.
The summary of typical inventions among those disclosed in this specification will be explained as follows.
The present invention is provided with at least one input terminal, at least one output terminal, a fixed delay granting means for granting, to the input signal, the predetermined delay corresponding to the period from the time when a signal is inputted to the input terminal to the time when a signal is outputted from the output terminal, a variable delay circuit provided with a delay time control terminal for giving a certain delay time to the input signal depending on a control voltage applied to the delay time control terminal and then outputting such signal having a certain delay time, a duty adjusting circuit provided with a duty control terminal for adjusting a duty ratio by changing a pulse width of the input signal depending on the control voltage applied to the duty control terminal, a delay time control means for generating the delay time control voltage and a duty control means for generating a control voltage applied to the duty control terminal.
According to the means explained above, since the duty adjusting circuit is provided independent of the variable delay circuit, the duty ratio can be adjusted without considering the variable delay circuit of the individual circuit system and therefore a degree of freedom for design becomes high and performance of the clock generation circuit is never limited with the performance of the variable delay circuit. Moreover, since the duty adjusting circuit adjusts the duty ratio by varying the pulse width of the signal, the size of circuit may be reduced in comparison with that of the system for adjusting the duty ratio by respectively controlling the phases of the rising edge and falling edge of the input signal with the individual DLL circuits having respective variable delay circuits.
The fixed delay granting means is constituted to grant, to the input signal, a fixed delay corresponding to the sum of the delay generated in the signal path up to the variable delay circuit from the input terminal and the delay generated in the signal path up to the output terminal from the variable delay circuit. Thereby, the internal clock signal, which is synchronized with the externally inputted clock signal and gives the timing to output the desired signal depending on the changing point of synchronization, can be generated.
Moreover, the delay time control means is comprised of a phase comparison circuit for comparing the phase of the signal outputted from the fixed delay granting means with the phase of the signal inputted to the variable delay circuit to output the signal depending on phase difference, and a control voltage generating means for generating a control voltage applied to the delay time control terminal based on the signal depending on the phase difference outputted from the phase comparison circuit. Thereby, automatic phase matching with a feedback loop also becomes possible.
Moreover, the duty control means is comprised of a second phase comparison circuit for comparing the phase of the signal in the output side of the variable delay circuit with the phase of the signal in the variable delay circuit to output a signal depending on the phase difference and a second control voltage generating means for generating a control voltage applied to the duty control terminal based on the signal depending on the phase difference outputted from the second comparison circuit. Thereby, the duty control means may be formed as the circuit structure similar to the delay time control means and accordingly the circuit design can be simplified.
Moreover, it is preferable to provide the structure that the duty adjusting circuit is provided in the successive stage of the variable delay circuit and the fixed delay granting means is provided in the successive stage of the duty adjusting circuit and the duty adjusting circuit can also vary, in addition, the pulse width to make identical the duty ratio of the signal outputted from the fixed delay granting means to that of the input signal of the variable delay circuit. Although it is also possible to comprise the duty adjusting function in the variable delay circuit, but the optimum design of each circuit is possible and performance of the circuit can further be enhanced by individually forming the duty adjusting circuit independent of the variable delay circuit. Moreover, the duty adjusting circuit can adjust the duty ratio through only variation of pulse width of the signal by providing the duty adjusting circuit in the successive stage side of the variable delay circuit and then providing the fixed delay granting means to the successive stage side of the duty adjusting circuit.
Moreover, it is also preferable that the delay time control means compares the phase of the rising edge or falling edge of the signal inputted to the variable delay circuit with the phase of the rising edge or falling edge of the signal outputted from the fixed delay granting means, to generate the control voltage applied to the delay time control terminal depending on the phase difference. The duty control means compares the phase of the falling edge or rising edge of the signal inputted to the variable delay circuit with the phase of the falling edge or rising edge of the signal outputted from the fixed delay granting means, to generate the control voltage applied to the duty control terminal depending on the phase difference. Thereby, the variable delay circuit controls amount of delay of clock with reference to one edge of the clock and the duty adjusting circuit controls the duty ratio by changing the pulse width of clock with reference to the other edge of clock. As a result, high precision phase control becomes possible for both the rising edge and falling edge of clock and the duty of the output clock can be accurately matched with the duty of the input clock.
The variable delay circuit is constituted to output a differential signal by delaying the input differential signal and also defines the signal outputted from the fixed delay granting circuit as the differential signal, while the duty control means is constituted to generate the control voltage applied to the duty control terminal based on the differential signal outputted from the fixed delay granting means. Thereby, even if delay of the variable delay circuit is different in the normal phase side and inverse phase side, accurate duty adjustment is possible.
Moreover, the phase comparison circuit forming the delay time control means is constituted to output a signal indicating lead or delay of the phases of two signal to be compared with each other and is also constituted to also include a phase lock determining means for determining the phase lock condition based on the signal indicating lead or delay of the phase so that the duty control means select the signal depending on the phase difference outputted from the second phase comparison circuit or the differential signal outputted from the fixed delay granting means based on the signal indicating the phase lock condition outputted from the phase lock determining means in view of generating the control voltage applied to the duty control terminal based on the selected signal.
The clock generation circuit comprises at least one input terminal, at least one output terminal, a fixed delay granting means for granting the predetermined delay corresponding to the period from the time when the signal is inputted to the input terminal to the time when the signal is outputted from the output terminal, a variable delay circuit including a delay time control terminal to give delay to the input signal depending on the control voltage applied to the delay time control terminal and then output such delayed signal, a duty adjusting circuit provided with a duty control terminal to adjust a duty ratio by changing the pulse width of the signal inputted depending on the control voltage to the duty control terminal, a delay time control means for generating a delay time control voltage and a duty control means for generating the duty control voltage. In this circuit, after the variable delay circuit adjusts the phase of signal based on any one of the rising edge or falling edge of the input signal, the duty adjusting circuit adjusts the duty ratio based on the other edge.
Thereby, the phase lock at the rising edge may be realized, even under the condition that amount of delay at the falling edge in the operation of the variable delay circuit becomes larger but amount of delay at the rising edge does not become large, by controlling the duty of the output clock to 50% until the phase is locked at the rising edge from the start of operation of the circuit.
In addition, in a semiconductor memory device including a clock generation circuit of the structure explained above, the semiconductor memory device which assures matching of the phases between the output data and the external clock with higher accuracy and has an extra setup time can be realized by forming the structure that the clock signal generated by inputting an external clock signal to the clock generation circuit is outputted as the timing signal.